1. Field of the Invention
The present invention relates to line drivers and, more particularly, to a line driver for producing operating condition invariant signal levels.
2. Description of the Related Art
A line driver is a device that drives a signal onto a transmission line, such as a local-area-network. Line drivers are typically associated with a specific network standard, such as the 100BASE-T standard (IEEE 100-Mbit/sec unshielded twisted-pair (UTP) 802.3), which defines the signaling rate, the signaling scheme, and the type of wiring of the network. One signaling protocol that is used with 100BASE-T-based networks is the MLT-3 (tri-level) signaling protocol which defines a 2Vpp signal that is output at 125 Mbits per second.
FIG. 1 shows a schematic diagram that illustrates a conventional 100BASE-T MLT-3 line driver 100. As shown in FIG. 1, driver 100 includes a transmit circuit 110 which has a pair of differential outputs OUT+ and OUT-, and a transformer 112 which has a pair of inputs IN+ and IN- that are connected to the outputs OUT+ and OUT-. In addition, transformer 112 also has a pair of transmission outputs TX+ and TX- that are connected to a transmission line 114, such as a 100-ohm line. Further, transformer 112 has a center tap connected to a power supply voltage Vcc.
As additionally shown in FIG. 1, circuit 100 includes a first resistor R1 which is connected between the power supply voltage Vcc and the output OUT+, and a second resistor R2 which is connected between the power supply voltage Vcc and the output OUT-. Resistors R1 and R2 each have a resistance that is equal to one-half the impedance of the transmission line, i.e. 50 ohms.
FIG. 2 shows a schematic diagram that illustrates a conventional transmit circuit 200. As shown in FIG. 2, circuit 200, which represents a first example of an implementation of circuit 110, includes a first transistor Q1 which has a drain connected to the output OUT+, a gate connected to receive a first signal SS1, and a source. Further, circuit 200 also includes a second transistor Q2 which has a drain connected to the output OUT-, a gate connected to receive a second signal SS2, and a source.
In addition, circuit 200 further includes a current source 210 which is connected between transistors Q1 and Q2, and ground. Current source 210, in turn, includes a tail current transistor Q3 which has a drain connected to the sources of transistors Q1 and Q2, a gate, and a source connected to ground.
Current source 210 also includes a mirroring transistor Q4 which has a drain, a gate connected to the gate of transistor Q3 and the drain of transistor Q4, and a source connected to ground. Transistor Q3 is formed to be A times larger than transistor Q4. Further, a bandgap current source BG outputs a compensated current to transistors Q3 and Q4 that defines the gate-to-source voltages of transistors Q3 and Q4. Since the gate-to-source voltages are defined by a compensated current, the gate-to-source voltages are substantially independent of variations in the power supply voltage Vcc.
FIGS. 3A-3E are timing diagrams that illustrate the operation of driver 100 of FIG. 1 when utilizing transmit circuit 200 of FIGS. 2 and the MLT-3 signaling protocol. The MLT-3 signaling protocol defines three signal levels which correspond to three of the logic states defined by the first and second signals SS1 and SS2.
As shown in FIGS. 3A-3D, the first signal level occurs when the signal SS1 has a logic low and the signal SS2 has a logic high such that transistor Q1 is turned off and transistor Q2 is turned on. Under these conditions, current source 210 pulls a current I through resistor R2 which sets up a voltage on input IN- that is less than the power supply voltage Vcc. (The voltage on input IN- is less than the power supply voltage Vcc since the voltage is equal to the power supply voltage Vcc less the voltage drop across resistor R2.)
At the same time, the action of transformer 112 causes a complementary voltage, which is greater than the power supply voltage Vcc, to appear on the input IN+. The voltage on input IN+ is greater than the power supply voltage Vcc by the same magnitude that the voltage on input IN- is less than the power supply voltage Vcc. Thus, a positive voltage is applied across the inputs IN+ and IN-.
The second signal level occurs when the signal SS1 has a logic high and the signal SS2 has a logic low such that transistor Q1 is turned on and transistor Q2 is turned off. Unlike the previous example, current source 210 now pulls the current I through resistor R1 which sets up a voltage on input IN+ which is less than the power supply voltage Vcc. (As in the previous example, the voltage on input IN+ is less than the power supply voltage Vcc since the voltage is equal to the power supply voltage Vcc less the voltage drop across resistor R1.)
At the same time, the action of transformer 112 causes a complementary voltage, which is greater than the power supply voltage Vcc, to appear on the input IN-. (As above, the voltage on input IN- is greater than the power supply voltage Vcc by the same magnitude that the voltage on input IN+ is less than the power supply voltage Vcc.) Thus, a negative voltage, which has a polarity opposite to the polarity of the positive voltage, is applied across the inputs IN+ and IN-.
The third signal level occurs when the signals SS1 and SS2 both have logic highs such that transistors Q1 and Q2 are both turned on. In this case, current source 210 pulls one-half of the current I through both resistors R1 and R2 which sets up substantially equivalent voltages on inputs IN+ and IN-. The action of transformer 112, in turn, forces the voltages on inputs IN+ and IN-to both be substantially equal to the power supply voltage Vcc.
In addition, as shown in FIG. 3E, a voltage COM at the drain of tail current transistor Q3 varies as transistors Q1 and Q2 are turned on and off. The variation results from the difference in resistance provided by transistor Q1 when transistor Q1 sinks all of current I, and when transistor Q1 sinks only one-half of current I. The variation also results from the difference in resistance provided by transistor Q2 when transistor Q2 sinks all of current I, and when transistor Q2 sinks only one-half of current I.
One of the disadvantages of transmit circuit 200 is that transistor Q3 does not have a high enough output impedance. A lower output impedance means that variations in the power supply voltage Vcc lead to variations in the steady state peak-to-peak differential voltage (V.sub.OD) of transmit signals TX+ and TX-.
Although the gate-to-source voltages of transistors Q3 and Q4 are substantially independent of variations in the power supply voltage Vcc, the voltage on the drain of transistor Q3 is not independent of the power supply voltage Vcc. For example, when the first signal level occurs, the signal SS1 has a logic low and the signal SS2 has a logic high, which is equal to the power supply voltage Vcc. As a result, the voltage on the drain of transistor Q3 is equal to the power supply voltage Vcc less the gate-to-source voltage of transistor Q2, i.e., Vcc-V.sub.GS Q2. Thus, variations in the power supply voltage Vcc cause variations in the drain voltage of transistor Q3.
When the variations in the drain voltage of transistor Q3 are combined with the low output impedance of transistor Q3, variations in the drain voltage of transistor Q3 lead to variations in the current I. Variations in the current I lead to variations in the voltages at outputs OUT+ and OUT- which, in turn, cause the voltages of the transmit signals TX+ and TX- to also vary. Thus, variations in the power supply voltage Vcc and a low output impedance cause variations in the transmit signals TX+ and TX-.
Variations in the transmit signals TX+ and TX- can be reduced to fall within the MLT-3 specification by simply increasing the output impedance of current source 210. One way of increasing the output impedance is to cascode the current source. FIG. 4 shows a schematic diagram that illustrates a conventional transmit circuit 400.
As shown in FIG. 4, circuit 400, which represents a second example of an implementation of transmit circuit 110 of FIG. 1, includes transistors Q1 and Q2 configured as shown in FIG. 2, and a current source 410 which is connected between transistors Q1 and Q2, and ground, as a high-swing cascode circuit. Current source 410 includes a first tail current transistor Q31 which has a drain connected to the sources of transistors Q1 and Q2, a source, and a gate; and a second tail current transistor Q32 which has a drain connected to the source of transistor Q31, a source connected to ground, and a gate.
Current source 410 also includes a first mirroring transistor Q41 which has a drain, a gate connected to the gate of transistor Q31, and a source; and a second mirroring transistor Q42 which has a drain connected to the source of transistor Q41, a gate connected to the gate of transistor Q32 and the drain of transistor Q41, and a source connected to ground. Current source 410 additionally includes a bias transistor Q5 which has a drain, a source connected to ground, and a gate connected to the gates of transistors Q31 and Q41, and to the drain of transistor Q5. Transistors Q31, Q32, Q41, and Q42 are A times larger than transistor Q5.
Further, a bandgap current source BG outputs a compensated current to transistors Q32 and Q42 which sets the gate-to-source voltages of transistors Q32 and Q42. In addition, a bias current source BI outputs a bias current, which is approximately equal to the compensated current, to transistors Q31, Q41, and Q5. The compensated current sets the gate voltages of transistors Q31, Q41, and Q5 to 2V.sub.GS -Vt (when the voltages at the drains of transistors Q32 and Q42 are equal to V.sub.GS -Vt).
In operation, current source 410 performs the same as current source 210, except that there is less variation in the transmit signals TX+ and TX- due to variations in the power supply voltage Vcc. Current source 410 still suffers from the same problem that current source 210 suffers from; namely, that the voltage on the drain of transistor Q31 is equal to the power supply voltage Vcc less the gate-to-source voltage of either transistor Q1 or Q2 when one of the transistors is on and the other is off. Thus, variations in the power supply voltage Vcc cause variations in the drain voltage of transistor Q31.
Current source 410 has less variation in the transmit signals TX+ and TX- due to variations in the power supply voltage Vcc because current source 410 has a larger output impedance (R.sub.o) than current source 210. Any change in the power supply voltage Vcc causes a current error that is equal to .DELTA.I=.DELTA.Vcc/R.sub.o. Since the output impedance of circuit 410 is higher than the output impedance of circuit 210, circuit 410 reduces variations in the transmit signals TX+ and TX- more than circuit 210.
One of the disadvantages of current source 410, however, is that the silicon area consumed by current source 410 is approximately six times (6.times.) as large as that consumed by current source 210. In addition, current source 410 requires about twice the headroom as that required by current source 210. Thus, there is a need for a line driver that reduces variations in the transmit voltages TX+ and TX- that result from variations in the power supply voltage without requiring the large size of current source 410 of transmit circuit 400.